Apparatus for detecting noise in the measurement of very small resistance

ABSTRACT

A pair of a first and a second R-C integrating circuits connected in series. A first switch S 1  supplies a first combined voltage E 1  +E 3  of a first positive threshold voltage E 1  and a positive initial set up voltage E 3  to a first capacitor in the first R-C circuit, and a second switch S 2  supplies a second capacitor with a second combined voltage of a second positive threshold voltage E 2  with a negative initial set up voltage -E 4 . The switches S 1  and S 2  are closed before the input of the signal to be measured. The switches are opened after the input of the signal. A first comparator compares a first discharged voltage output from the first capacitor and the first threshold voltage E 1 , and a second comparator compares a second discharged voltage output from the second capacitor and the second threshold voltage E 2 . A logic circuit is connected to the output terminals of the first and second comparators, respectively, and determine in conjunction with a timing circuit whether the first and second discharged voltages are within a range between the first threshold voltage E 1  and second threshold voltage E 2  within a predetermined time period of the input of the signal to be measured, so as to provide an indication to judge the right time for resistance measurements.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an ohmmeter of the type capable ofmeasuring small electric resistance in units of milliohms.

2. Description of the Prior Art

Electrical resistance is the rate of the potential difference betweenthe ends of a conductor to be measured to the electrical current flowingin the conductor. With respect to FIG. 1, which is a diagram of a modelcircuit showing the relationship of electrical current I with thevoltage difference V across a resistor R_(x) is expressed by theformula:

    R=V/I                                                      (1)

In the diagram, e is an alternating current source generating a currentof known value I, V_(o) is a voltmeter giving readings of voltagedifference V, and R_(x) is a resistor or conductor supposed to have aresistance R to be measured.

With the progress of precise electrical applications, it has becomeincreasingly necessary to determine very small magnitudes of resistance.

Measurements of resistance in minute units naturally involves dealingwith correspondingly smaller denominations of amperage and voltage.Measurements of infinitesimal magnitudes have normally involved usingattenuators and amplifiers with high and stable gains, such asoperational amplifiers.

However, these conventional methods have been found to pose problems.The operational amplifiers have generated noises having serious effectson the readings.

Some attempts have been made to eliminate the above drawback. Forexample, as in most cases, a noise filter has been connected to theamplifier. However, the use of noise filters have failed to help much.

Assuming that an ideal measuring instrument is used to determine thevoltage difference V across a conductor with a resistance of I microhmwhen an alternating current at 1 milliampere is applied to theconductor, the theoretical voltage difference V should be 1 nanovolt, or1×10⁻⁹ =1×10⁻⁶ ×1×10⁻³, according to the equation V=RI obtained byadjusting the equation 1 above for V. However, in actual practice, thegeneration of noises must be considered. Using statistical mechanics,which looks into the mechanical properties of large assemblies ofparticles or components in terms of statistics, noise Vn in volts forvoltage difference nV to be measured is given by the formula:

    Vn=2√kTRΔfnV                                  (2)

where K is Boltzmann's constant, T is absolute temperature, R isconductor resistance and Δf is the noise range of the instrument usedfor measuring voltage differences.

Even when one of those most advanced operational amplifier producing theleast noises is used, for a very small voltage difference of 1×10⁻⁹, theamplifier would develop a noise level of about 1.2√ΔfnV, a level almostapproaching the difference to be measured, using the equation 2 above,where 2/kTR is known to be 1.2×10⁻⁹. If the noises generated are thathigh, accurate measurements of resistances through amplification ofvoltage differences would almost be impossible, particularly whenmagnitudes involved are very small.

Various improvements have been proposed to eliminate the abovedifficulty. For example, a phase detection circuit 8, as illustrated inschematic form in FIG. 2, may be used. The phase detection circuit 8comprises an inverter circuit 10 and a R-C circuit 12.

With respect to FIG. 2, when a voltage difference Vo to be measured isapplied to the detection circuit 8 at its input terminal 8a, theinverter circuit 10 splits each cycle of the input signal Vo into afirst and a second half wave. The first halves of positive polarity ofthe signal Vo appear, as they are, on a first output terminal 8b of theinverter circuit 10. A combination of a operational Amplifier A and apair of resistors R₁ and R₂ inverts the second halves in polarity, andoutputs the inverted second half waves through a second output terminal10c. A switch means S alternates between the first output terminal 10band second output terminal 10c to integrate the noniverted first halvesand inverted second halves into a train of whole wave cycles. In thisprocess, noises are superimposed onto the voltage signal Vo beingmeasured. The R-C circuit 12, which is comprised of a capacitor C₁₂ anda resistor R₁₂, is connected to the inverter circuit 10 to achieve areduction in the noise signal superimposed over the voltage signal to bemeasured. The R-C circuit 12 outputs the result of electric chargestorage at its output terminal 12h as a voltage level e_(o), after noisereduction, which would be a close approximation of the voltage signal Voto be measured. The process of this reduction will be explained in moredetail with reference to the diagrams in FIG. 3.

The diagrams shown in FIG. 3 are the waveform of difference voltagesignals, with times taken along the horizontal axis. FIG. 3(a) is thewaveform of the voltage difference Essin ωt to be measured. The waveformof FIG. 1 is superimposed onto the waveform of the noise Ensin (αt+θ)generated, as shown in FIG. 3(b), to develop a combined waveform Essinωt Ensin (αt+θ), as indicated in FIG. 3(c). In this description, thenoise is shown as a sine wave signal for the sake of simplicity ofexplanation, although noises in actual cases come in far morecomplicated waveforms. On the output terminal of the inverter circuit10, a superimposed signal similar to the one in FIG. 3(d) would appearas a result of inversing the second half of each wave cycle in thewaveform of FIG. 3(c).

The inversed voltage signal of FIG. 3(d) is expressed as E_(s) sinωt+E_(n) sin (αt+θ) when (2n-1)π/ω>t2(n-1)/ω, and -{E_(s) sin ωt+E_(n)sin (αt+θ)} when 2nπ/ω>t>2(n-1)π/ω, where n: integer, ω: frequency, α:frequency of noise voltage, θ: phase of noise voltage.

Since the signal shown in FIG. 3(d) is inversed at time intervals π/ω,that part of it which constitutes the voltage signal Vo to be measuredis expressed as Essin ωt in absolute value.

However, although the part of the inversed FIG. 3(d) signal thatconstututes the noise voltage, which is also inversed at time intervalsof π/ω, its time average would come almost zero since such noise cannormally occur in wide ranges of amplitude and frequency.

In normal condition, the time average of the output voltage signal e_(o)from the inverter circuit 10 of FIG. 2 is expressed as 2/π·Es.

It might be important to note here that, instead of inverting thevoltage signal Vo to be measured in the manner as described above,full-wave rectification of the superimposed voltage of FIG. 3(c) toobtain a waveform as shown in FIG. 3(e) would mean irrelevance. Suchfull-wave rectification would produce an average of Essin ωt+Ensin(αt+θ) in absolute value, including the noise signal component Essin(αt+θ)

The phase detection circuit 8 shown in FIG. 2 yields an average of theinversed voltage signal of FIG. 3(d) through the function of thecapacitor C₁₂.

The voltage signal that appears on the output terminal of the capacitorC₁₂ comes Essin ωt, an absolute value, since the noise component isreduced to zero through integration by the capacitor.

Letting the voltage signal e_(i) input to the phase detection circuit 8Essin ωt, the voltage signal e_(o) appearing on the output terminal ofthe capacitor C₁₂ is given by a series of computations as follows:

When the frequency ω for the signal is π/ω>t>0, e_(o) is expressed asfollows using the Laplace transformation:

    e.sub.o =Es/(1+ω.sup.2 C.sup.2 R.sup.2){(sin ωt-ωCR cos ωt)+ωCRe.sup.-t/RC }                          (3)

when

C: capacitance value of capacitor, C₁₂

R: resistance value of resistor R₁₂

e: euler's constant

When 2π/ω≧t≧π/ω, e_(o) is expressed using the theorem ofsuperimposition:

    e.sub.o =Es/(1+ω.sup.2 C.sup.2 R.sup.2){-(sin ωt-ωCR cos ωt)+ωCR(1+2e.sup.π/ωCR)e.sup.-t/RC } (4)

Generally, in the relation (n-1)π/ω<t<nπ to determine the value for n,fthe voltage signal e_(o) is:

(1) for the value "n" being an odd number,

    e.sub.o =Es/(1+ω.sup.2 C.sup.2 R.sup.2){(sin ωt-ωCR cos ωt)+ωCR(1+2e.sup.π/ωCR +2e.sup.2π/ωCR . . . +2e.sup.(n-1)π/ωCR)e.sup.-t/RC },

and, (2) for the value "n" being an even number,

    e.sub.o =Es/(1+ω.sup.2 C.sup.2 R.sup.2){-(sin ωt-ωCR cos ωt)+ωCR(1+2e.sup.π/ωCR +2e.sup.2π/ωCR . . . +2e.sup.(n-1) π/ωCR)e.sup.-t/RC },

Combining the equations (5) and (6) above gives:

    e.sub.o =Es/(1+ω.sup.2 C.sup.2 R.sup.2)[±(sin ωt-ωCR cos ωt)+ωCR{(2e.sup.nπ/ωCR -2)/(e.sup.π/ωCR -1)-1}e.sup.-t/RC ]                                       (7)

Of the double signs ± in the equation 7 above, the "+" is for the value"n" being an odd numer, and the "-" is for the value "n" being an evennumber.

In actuality, since voltage signals to be measured normally are designedgreater in frequency ω and time constants R, C, so ωRC>1.

Thus, the last term in the righthand side of the equation 7 above can besimplified as follows: ##EQU1##

For the equation 8 above, e^(n)π/ωCR-t/RC ≈1, e.sup.π/ωCR-t/RC ≈1.

    e.sup.π/ωCR ≈1+π/ωCR

Putting the value for the above-mentioned term into the equation 7 forthe capacitor output voltage signal e_(o), and further approximationyields:

    e.sub.o =2Es/π(1-e.sup.-t/RC)                           (9)

In the above computation, the value for the first term of the equation 7is ignored because it is very small compared with the value for the lastterm.

In other words, the value of the transient voltage signal e_(o)appearing on the output terminal of the capacitor C₁₂ of FIG. 2 isobtained by multiplying the term "1-e^(-t/RC) " of the equation 7 withthe average value 2Es/π that is reached by full-wave rectification ofthe voltage signal input to the phase detection circuit 8.

Accordingly, when the inversed voltage signal ein having value |Essinωt| appearing on the output terminal of the phase detection circuit 8 inFIG. 2 is applied to the capacitor C₁₂, the system would always take adelay of fixed duration before the output terminal of the capacitorproduces constant voltage signals whose values are or close 2Es/π. Inthis case, the noise voltage is ignored since a time average of itsvalue becomes almost zero.

Furthermore, it is well known that the noise to signal ratio (S/N), theratio of the magnitude of the signal to that of the noise, for thecircuit in FIG. 2 is expressed by the following formula:

    S/N=2/τfoEs/EN,                                        (10)

where

fo: the frequency of the voltage signal being measured, which isequivalent to ω/2π for the aforesaid voltage signal Essin ωt

τ=CR: time constants by C₁₂, R₁₂ in the circuit of FIG. 2

E_(n) : the amplitude of the noise signal

For example, when the voltage signal is input to the phase detectioncircuit at a frequency of 1 kHz, the amplitude of the noise voltage Enthat would be produced even by one those most advanced amplifiers withthe least noise is as follows using the equation 2 above for noisevoltages:

    E.sub.n =1.2×/1,000≈38 nanovolts.

Normally, the value for fo is 1 kHz. When the value from the equation 9for S/N ratios is required to be 1, when the above value for fo, alongwith the aforesaid value for En is put into the equation, the value forτ must be 0.36 (in seconds). This means that the R-C circuit 12 must bedesigned such that the combined time constant for the capacitor C₁₂ andresistor R₁₂ is 0.36.

It thus follows that for an R-C circuit such as shown in FIG. 2 toproduce its output voltage within a 99% target accuracy range of thevoltage signal Es to be measure, the value for e^(-t/)τ must be 0.01,based on the relation Es(1-e^(-t/)τ) =0.99E.

This means that the operator has to wait about 1.7 seconds before theresult of measurement at about 1% error is obtained.

SUMMARY OF THE INVENTION

The present invention has been proposed to eliminate the drawback of thedifficulties with the prior art micro ohmmeters using phase detectioncircuits.

It is therefore a primary object of the present invention to provide amicro ohmmeter capable of fast readings, with the elimination of timedelays in measurement.

The present invention proposes an improvement in ohmmeters using a phasedetection circuit consists of an inverter circuit to inverse the halfwave of each cycle of the voltage difference as a function ofresistances to be measured and an R-C circuit to integrate split halfwaves into a train of whole cycles. The improventment comprises a pairof integrating R-C circuit connected in parallel. A first thresholdvoltage combined with a first initiatially set up voltage E₁ +E₃(wherein E₁ : first threshold voltage, E₃ : first set up voltage) ispre-charged into a first capacitor in the first integrating R-C circuitthrough a first switch means S₁ to be discharged when a voltagedifference signal to be measured is applied to the system. A firstcomparator compares the output from the capacitor with the thresholdvoltage E.

A combined second threshold voltage with a second initilly set upvoltage E₂ -E₄ (wherein E₂ : second threshold voltage, -E₄ : second setup voltage) is also pre-charged into a second capacitor in the secondintegrating R-C circuit through a second switch mians S₂, also to bedischarged at the application of the voltage signal to be measured. Asecond comparator compares the output of the capacitor in the second R-Ccircuit with the second threshold voltage E₂. A timing circuit isconnected to determine each of the voltage outputs from the first andsecond capacitors is within the range of their associated thresholdvoltage E₁ and E₂ (in the other words between E₁ and E₂) within apredetermined time period of the application of the voltage signal to bemeasured.

BRIEF EXPLANATION OF THE ACCOMPANYING DRAWINGS

FIG. 1 is a schematic of a basic circuit for measuring resistances usinga voltmeter;

FIG. 2 is a schematic of a basic circuit designed for noise reduction inresistance measurements, comprising an operational amplifier forpolarity inversion, a signal selector switch and an integrating circuit;

FIG. 3 shows a group of diagrams showing the waveform of voltage signalsin the different stages of resistance measurement in which:

FIG. 3(a) is a voltage difference signal to be measured;

FIG. 3(b) is a noise signal developed by measuring instruments;

FIG. 3(c) is a diagram indicating the superimposition of the voltagesignal of FIG. 3(a) and noise signal of FIG. 3(b);

FIG. 3(d) is a diagram showing the result of superimposition of thenon-inverted first half of each cycle of the splited superimposed signalof FIG. 3(c) and the second half that was inversed by a phase detectioncircuit;

FIG. 3(e) is a diagram showing the rectification of the voltage signalshown in FIG. 3(c);

FIG. 4 is a schematic showing a preferred embodiment of the presentinvention using pairs of integrating circuits and comparators;

FIG. 5 is a schematic of a logic circuit designed to determine the valuefor P and Q, where P=(A₁ +A₂)T and Q=(A₁ +A₂)T; and

FIGS. 6(a) and 6(b) are diagrams indicating the value for A₁, A₂, T, Pand Q when the voltages appearing at the output terminals of the twocapacitors in the paired R-C circuit are in the range of theirassociated threshold voltage and out of the range of their associatedthreshold voltage, respectively

DETAILED DESCRIPTION OF THE INVENTION

Referring first to FIG. 4, which is a schematic representation of amicro ohmmeter according to a preferred embodiment of the presentinvention, a noise reduction circuitry 12 include a pair of a first R-Cintegrating circuit 14 and a second R-C integrating circuit 16 connectedin parallel. The noise reduction circuitry 12 is connected to acombination of a switch means S and a inverter circuit similar to theswitch means S and the circuit 10 described earlier in association withFIG. 2. The inverter circuit may be any known type capable of splittingeach cycle of an alternating voltage signal into a non-inverted firsthalf wave and an inverted second half wave, and the switch meanscombines the split half waves into a train of whole cycles.

The first R-C circuit 14 comprises a first resistor R₁₄ and a firstcapacitor C₁₄. Similarly, the second R-C circuit 16 consists of a secondresistor R₁₆ and a second capacitor C₁₆.

The first capacitor C₁₄ of the first R-C circuit 14 is supplied throughits input stage with electricity by a positive initialization voltage E₃and a first threshold voltage E₁, connected in series, through a firstswitch means S₁. The first switch means S₁ charges the first capacitorC₁₄ with a combined voltage of E₁ and E₃. Also, a negativeinitialization voltage E₄ and a second threshold voltage E₂ areconnected in series, and are added to be fed to the second capacitor C₁₆through its input stage in the second R-C circuit through a secondswitch means S₂. As with the first switch means S₁, the second switchmeans S₂ charges its capacitor in a timed relationship with the input ofthe inversed voltage signal V_(o) to the noise reduction circuit 12, aswill later be described.

The first and second threshold voltages E₁ and E₂ must be set to differin magnitude than each other so as to define in combination a range forthe reason that will be described. In this particular embodiment, thefirst threshold voltage E₁ is greater than the second E₂ for the sake ofdescription. However, this assumption should not be taken to give alimitation to the embodiment of the present invention.

The first threshold voltage E₁ is also connected to a positive inputterminal of a first comparator 18. The output stage of the firstcapacitor C₁₄. Also, the second threshold voltage E₂ is linked to anegative input terminal of a second capacitor 20. A positive inputterminal of the second comparator 20 is connected to the output stage ofthe second capacitor C₁₆.

It is so designed that the first comparator 18 and second comparator 20cooperate to determine the output signal appearing on the output stageof each of the first and second capacitors C₁₄ and C₁₆ are within therange between the first threshold voltage E₁ and second thresholdvoltage E₂ within a predetermined duration of time following theentrance of an inversed voltage signal V_(s) into the noise reductioncircuit 12 in the manner as will later be described in detail.

The effect that can be produced by the above-mentioned arrangement oftwo comparators 18, 20 respectively linked to R-C integrating circuit14, 16 to operate in conjunction with separate threshold voltages E₁,E₂, can be provided by a variety of circuit designs. Therefore, it is tobe noted that the present invention should not be considered to belimited to the illustrated embodiment.

Connected to the output of each of the comparators 18 and 20 is a logiccircuit 24 which includes a first AND gate 26 and a second AND gate 28.The logic circuit 24 has a first output terminal Go and a second outputterminal NoGo. The first AND gate 26 has a first input terminal G₁, asecond input terminal G₂ and a third input terminal G₃. The first inputterminal G₁ is connected to the output terminal of the first comparator18. Also, the output terminal of the second comparator 20 is connectedto the second input terminal G₂ of the AND gate 26, whose third inputterminal G₃ is connected to a timing circuit 22 through a first inverter30.

The timing circuit 22 supplies the third input terminal G₃ of the ANDgate 26 with timing signals T. The timing circuit 22 is designed so thatthe value of its signal T is "0" when it is within a predetermined timeperiod of the application of an inversed voltage signal V_(s) to thecircuit 12, and "1" following the lapse of the predetermined period.Because of the interposition of the inventer 30, the first AND gate 26always receives an inversed signal T when the timing circuit 22 inputsits timing signal T.

The first comparator 18 feeds the first input terminal G₁ of the firstAND gate signals A₁. The value of the signals A₁ is either "1" toindicate that the first threshold voltage E₁ is higher than the voltagesignal from the output stage of the first capacitor C₁₄ or "0" to showthat the difference is reversed. Similarly, the second comparator 20supplies the first AND gate 26 through its second input terminal G₂ withsignals A₂. The signals A₂ have either a logic 1 value when the secondthreshold voltage E₂ is lower than the voltage from the output stage ofthe second capacitor C₁₆ or a logic 0 value when relation is to thecontrary.

With the above arrangement, the output of the first AND gate, whichappears on the output terminal Go of the logic circuit 24, is thelogical product P of the three input signals A₁, A₂ and T through itsinput terminals G₁, G₂ and G₃. In this embodiment, the logical productP(=A₁ ·A₂ ·T) is "1" to indicate that the voltage signal from each ofthe output stages of the first and second capacitors C₁₄ and C₁₆ fallswithin the range between the first threshold voltage E₁ and secondthreshold voltage E₂ within the predetermined time period.

When the logical product P is "0", at least one of the aforesaidparameters is the opposite.

The timing circuit 22 is directly linked to a first input terminal g₁ ofthe second AND gate 28, which has its second input terminal g₂ connectedto the output terminal of the first AND gate 26 through a secondinverter 32. The value of the timing signal T component that the secondAND gate 28 receives through its second input terminal g₂ must always bethe same as that through teh first input terminal g₁, due to theconnection of the two inverters 30 and 32, providing both the inputsignals A₁ and A₂ each have a value "1". Thus, the output of the secondAND gate 28 is the logical product Q of the timing signal T and the sumof the not of the output signal A₁ and the not of the output A₂ from thefirst and second comparators 18 and 20, respectively, expressed as Q=(A₁+A₂)·T.

In other words, the output of the second AND gate, which is linked tothe second output terminal NoGo of the logic circuit 24, determines thateither of the voltage signals from the output stages of the first andsecond capacitors C₁₄ and C₁₆ is not within the threshold voltage rangebetween E₁ and E₂ after the lapse of the predetermined time period. Toillustrate, when the logical product Q is "1", it means that at leastone of the capacitor output voltages is within the reference voltagerange after the predetermined time period. When Q=0, the situation is tothe contray.

The same result that satisfies the above logical porduct Q=(A₁ +A₂)·Tcan be provided by a variety of circuit designs in which each of theoutput of comparators 18 and 20 is connected to a two-input NOR gatewhose output is connected t the one input of an two-input AND gate, withthe timing circuit 22 being connected to the other input of the ANDgate. The output of the AND gate achieves that logical product.

FIG. 5 is a schematic of a logic circuit 24_(A) developed as amodification of the logic circuit 24 of FIG. 4, in which like componentsare designated by like numerals. In this modification, the output ofeach of the paired comparators 18 and 20 is connected to a first and asecond input terminals of an OR gate 34 whose output terminal is linkedto a first input terminal of an AND gate 36. The timing circuit 22 hasits output connected to a second input terminal of the AND gate 36. TheAND gate 26 receives through its three input terminals signals A₁, A₂and T from the paired comparators 18, 29 and the timing circuit 22,respectively, in the same manner as in the logic circuit 24 of FIG. 4.With this arrangement, it would be clear to those versed in the art thatthe output of the AND gate, which appears on one output terminal Go ofthe circuit 24_(A), is the logical product P of the signals A₁, A₂ andT, which is expressed as P=A₁ ·A₂ ·T. Similarly, the output of the otherAND gate 36, which comes out from the output terminal NoGo, is thelogical product Q of the timing signal T and the sum of the signals A₁and A₂, expressed as Q=(A₁ +A₂)·T.

There can be other forms of circuit structures that provide the sameeffect as the illustrated embodiments. The present invention should beconsidered to cover all possible modifications conceivable bases on theembodiments in FIGS. 4 and 5.

Since the construction of the noise reduction circuit 12_(A) isdescribed, the operation of the circuit will be explained in full detailaccording to the present invention in conjunction with FIGS. 4 and 5.

With respect to FIG. 4, in operation, before a signal voltage V_(s) tobe measured is passed into the noise reduction circuit 12, thepairedswitches S₁ and S₂ are simultaneously closed. As a result, thefirst capacitor C₁₄ is charged with a combined voltage (E₁ 30 E₃) offirst threshold voltage E₁ with negative intialzation voltage E₄. Also,the second capacitor C₁₆ is charged with a combined voltage (E₂ -E₄) ofpositive second threshold voltage E₂ and negative intialization voltageE₄.

Upon the application of the signal voltage V_(s), which is thesuperimposition of a signal voltage E_(s) to be measured and a noisevoltage E_(n), to both the first R-C integrating circuit 14 (composed ofR₁₄ and C₁₄) and second R-C integrating circuit 16 (composed of R₁₆ andC₁₆), the switch S₁ and S₂ are both opened simultaneously. In thisprocess, the noise reduction circuit 12 achieves a reduction in thenoise signal component E_(n) in the voltage signal V_(s) by integration.

Letting V_(s) =2/πE_(s), the voltage V₁ appearing on the output stage ofthe first capacitor 14 upon discharge is;

    V.sub.1 =(E.sub.1 +E.sub.3).sub.e.sup.-t/τ.sbsp.1 +(1-e.sup.-t/τ.sbsp.1)V.sub.s                         (11)

where τ₁ =R₁₄ ·C₁₄ (product of capacitor C₁₄ and resistor R₁₄ in thefirst R-C circuit 14,)

Likewise, the voltage V₂ appering on the output stage of the secondcapacitor C₁₆ upon discharge is:

    V.sub.2 =(E.sub.2 -E.sub.2)e.sup.-t/τ.sbsp.2 +(1-e.sup.-t/τ.sbsp.2)V.sub.s                         (12)

where τ₂ =R₁₆ ·C₁₆ (product of capacitor C₁₆ and resistor R₁₆ in thesecond R-C circuit 16,)

When the voltage signal V_(s) to be measured has fallen within the rangebetween the first and second threshold voltages E₁ and E₂, as shown inFIG. 6(a), the discharged voltages V₁ and V₂ appearing on the outputstages of the first capacitor C₁₄ and second capacitor 16 shouldnecessarily reach their associated threshold voltages E₁ and E₂,respectively, within some time of the input of the that signal V_(s). Ifthis time is shorter than the predetermined time during which the timingcircuit 22 is generating a logic 0 signal, the logical product P of thethree signals A₁, A₂ and T, which appears on the output terminal of thefirst AND gate 26, will be P=A₁ ·A₂ ·T=1. In this embodiment the logicalproduct P=1 means that the noise reduction circuit 12_(A) has achivedthe highest noise reduction in the superimposed voltage V_(s). Theoutput "1" may be connected through the output terminal Go of thecircuit 12_(A) to a suitable recording device which takes track ofvoltage readings at this moment.

However, if the voltage signal V_(s) to be measured has occured outsidethe threshold voltgage range between E₁ and E₂, say, above the firstthreshold voltage E₁, as shown in FIG. 6(a), it could never happen thatthe discharged voltage V₁ from the first capacitor C₁₄ reaches the firstthreshold voltage E₁.

In this case, the timing circuit 22 will eventually outrun thepredetermined time period, and produce a logic 1 signal. As a result,the logical product Q, which appearing of the second AND gate 28, isQ=(A₁ +A₂)·T=1. The logical product Q=1 means that the noise reductioncircuit 12 is in wrong condition to achieve an acceptable noisereduction. This output is conveyed through the output terminal NoGo ofthe circuit 12_(A) to a suitable means which disconnects the circuitfrom the recording device.

In the circuit shown in FIG. 2, the discharged voltage V from thecapacitor C₁₂ of the R-C integrating circuit 12 is V=E_(s) (1-e^(-t/)τ).Letting E_(s) be the voltage to be measured, if the value for V shouldbe such that V=(1-α)E_(s), the value for the aforesaid predetermind timeperiod T_(o) during which the timing circuit 22 generates a logic 0signal is required to be such that e^(-t/)τ =α, where α is the allowablerate of error of the discharged capasitor voltage to the voltage signalE_(s) to be measured. The value for α should therefore be 1% when thedischarged voltage is set to come 99% of the voltage signal E_(s).Generally, 1>>α>0. It thus follows that the value for T_(o) is:

    To=τ/log (1-α)                                   (13)

Using this basic concept for the noise reduction circuit 12_(A) of FIG.4 according to the present invention, the time in which the voltage V₁on the output of the capacitor C₁₄ reaches the first threshold voltageE₁ must satisfy the following equation:

    (E.sub.1 +E.sub.3)e.sup.-t/τ.sbsp.1 +(1-e.sup.-t/τ.sbsp.1)V.sub.s =E.sub.1                                                  (14)

The difference αE_(s) between the voltage signal E_(s) to be measuredand the first threshold voltage E₁ is:

    E.sub.1 -V.sub.s =αV.sub.s                           (15)

It thus follows that, letting T₁ the time in which the dischargedvoltage V₁ from the first capacitor C₁₄ reaches the first thresholdvoltage E₁, the value for T₁ using the equations 14 and 15 above, mustsatisfy the following equation:

    T.sub.1 =τ.sub.1 log {1+(1+/α)E.sub.3 /E.sub.1 } (16)

Similarly, the time in which the voltage V₂ appearing on the outputstage of the second capacitor C₁₆ reaches the second threshold voltageE₂ must meet the equation as follows:

    (E.sub.2 -E.sub.4).sub.e.sup.-t/τ.sbsp.2 (1-e.sup.-t/τ.sbsp.2)V.sub.s =E.sub.2                 (17)

The difference αV_(s) between the signal V_(s) to be measured and thefirst threshold voltage E₂ is:

    V.sub.s -E.sub.2 =αV.sub.s                           (18)

Likewise, it follows that, letting T₂ the time in which the discharge V₂from the output stage of the second capasitor C₁₆ reaches the secondthreshold voltage E₂, the value for T₂, using the equations 17 and 18above, must satisfy the equation as follows:

    T.sub.2 =τ.sub.2 log {1+(1/α-1)E.sub.4 /E.sub.2 }(19)

The time period T_(o), as solved by the equation 13 above, in which thevoltage discharged from the capasitor C₁₂ of the circuit 8 in FIG. 2will be compared with T₁ and T_(s) obtained by the equations 16 and 19.

Since E₁ >E₃, it follows that 1/α>1>1+(1+1/α)E₃ /E₁. Furthermore, sinceE₂ >E₄, then obviously 1/α>1>1+(1/α-1)E₄ /E₂.

Accordingly, T_(o) >>T₁ and T_(o) >>T₂.

It will be clear from the above that discharge of the capacitors C₁₄ andC₁₆ precharged with pairs of initialzation voltages E₃ and E₄ andthreshold voltages E₁ and E₂, upon the input of an inverted voltagesignal V_(s) to be measure, would allow the discharged voltage signalsto come close to the value for V_(s) (=2/πE_(s)), providing the signalV_(s) is within the range between E₁ and E₂, in a far shorter time inthe noise reduction circuit 12_(A) of this invention (FIG. 4) than inthe prior art devices such as the one in FIG. 2.

It will be appreciated from the above that the noise recution circuitaccording to the present invention can be effectively used inmeasurement of resistance of infinitesimal magnitudes, in whichconventional R-C intengating circuits, while achieving a reduction inthe noise component of the input signal comprised of the noisesuperimposed onto a signal to be measured, producing a capacitordischarged voltage at levels approacing the voltage signal to bemeasured.

What is claimed is:
 1. In an ohmmeter which includes a phase detectionmeans to split each cycle of a voltage signal to be measured into afirst and second series of half waves, an inverter means to inverse thesecond series of half waves, an integrating R-C circuit means to combinethe first and second series of half waves in such a manner as toachieved a reduction in the noise component of the superimposition ofnoise and a signal to be measured, the improvement comprising:theintegrating R-C circuit means comprising a pair of first R-C integratingcircuit and second R-C integrating circuit connected in parallel: afirst switch means S₁ adapted to charge a first capacitor in the firstR-C integrating circuit with a first combined voltage E₁ +E₃ of a firstpositive threshold voltage E₁ with positive initial set up voltage E₃ ;a second switch means S₂ adapted to charge a second capacitor in thesecond R-C integrating circuit with a second combined voltage E₂ -E₄ ofa second positive threshold voltage E₂ with negative initial set upvoltage -E₄, the first threshold voltage E₁ and second threshold voltageE₂ being set to differ in magnitude from each other so as to define athreshold voltage range, the first switch means S₁ and second switchmeans S₂ being actuated to close a supply circuit which in turn suppliesboth the first combined voltage E₁ +E₃ to the first capacitor, and thesecond combined voltage E₂ -E₄ to the second capacitor, respectively, apredetermined time before the entrance of a voltage signal to bemeasured, the first and second switch means being opened to break thesupply circuit upon the input of the voltage signal to be measured; afirst comparator connected to the first R-C integrating circuit andadapted to compare the first threshold voltage and a first outputvoltage discharged from the first capacitor; a second comparatorconnected to the second R-C integrating circuit and adapted to comparethe second threshold voltage and a second output voltage discharged fromthe second capacitor; a logic circuit connected to the first and secondcomparators and a timing circuit, the timing circuit adapted to supplytiming signals to the logic circuit, the logic circuit adapted todetermine whether the first and second discharged voltages are withinthe range of their associated threshold voltages E₁ and E₂ in a set timefollowing the input of the voltage signal to be measured in conjunctionwith the timing signal from the timing circuit.
 2. A device as set forthin claim 1, wherein the first comparator outputs a first logic signal A₁whose value is 0 when the discharged voltage output from the firstcapacitor is higher than the first threshold voltage E₁, the value forthe first logic signal being 1 when the discharged voltage from thefirst capacitor is lower than the first threshold voltage, the secondcomparator outputs a second logic signal A₂ whose value is 1 when thedischarged voltage output from the second capacitor is higher than thasecond logic threshold voltage E₂, the value for the second logic signalbeing 0 when the discharged voltage from the second capacitor is lowerthan the second threshold voltage E₂, and the timing circuit outputs alogic timing signal T whose value is 0 before a set time period lapses,the value of the timing logic signal being 1 after the lapse of the settime period, wherein the logic circuit comprises a first circuit partwhich computes the logical product P of the first logic signal A₁, thesecond logic signal A₂ and the not of the logic timing signal T, and asecond circuit part which computes the logical product Q of the logictiming signal T and the sum of the not of the first logic signal A₁ andnot of the second logic signal A₂, the logic circuit being linked to afirst output terminal which, when the logical product P computed by thefirst circuit part is 1, outputs a first signal indicating the righttime for resistance measurements, the logic circuit being linked to asecond output terminal which, when the logical product Q by the secondcircuit part is 1, outputs a second signal indicating the wrong time forresistance measurements.